1. Field of the Invention
The present invention relates to a contact and a wiring layer of a semiconductor device, and more particularly, the invention relates to contacts arranged in the minimum process dimensions represented by data transfer line contacts of a NAND type EEPROM and a NOR type EEPROM.
2. Description of the Related Art
As a structural example of a conventional wiring contact in a semiconductor device, an example of the NAND type EEPROM is shown in FIGS. 68 to 71. FIG. 68 is a plan view of a cell array, and FIGS. 69, 70, and 71 are cross sectional views taken along the lines 69—69, 70—70, and 71—71 of FIG. 68, respectively. The cell array is formed in a P-type well of a silicon substrate 1. In element regions arranged in a stripe shape electrically separated by element separating insulation films 2, a NAND type cell unit is formed of a plurality of nonvolatile memory cells. The plurality of nonvolatile memory cells are connected in series in a form such that an n-type source/drain diffusion layer 3 is shared by the adjacent memory cells.
The memory cell has a structure in which a floating gate 4 and a control gate 5 are deposited each other. The control gate 5 is formed to be patterned as a word line WL that is a continuous layer in one direction as shown in FIG. 68. Selection transistors are formed at both ends of the NAND cell unit, and gate electrodes 6 thereof are formed to be continuous patterns used as control gate lines SSL and GSL parallel to the word line WL.
A drain side end of the NAND cell unit and the diffusion layer 3 of the source side end are connected to first wiring layers 12a and 12b via conductor plugs (contact plugs) 11a and 11b embedded in an interlayer insulation film 10a, respectively. A first wiring layer 12b at the source side is provided as a common source line SL running in parallel to the word line WL, as shown in FIG. 68. The first wiring layer 12a at the drain side is a lead-out wiring (a connecting wiring) to the bit line and is connected to a bit line (BL) 13 formed on an interlayer insulation film 10b formed thereon.
When attention is paid to the contact 11a at the bit line side, as shown in FIG. 68, the contact 11a are formed in a circular (or elliptical) shape, and are arranged in a direction (a direction along the line 70—70) orthogonal to the wiring layer 12a. The arrangement pitch of the contacts 11a in the direction along the line 70—70 depends on the widths of the element region and element separation region. For example, assuming that the minimum process dimension is F, when the element regions are formed with 2F pitch, the arrangement pitch of the contacts 11a is 2F as well. On the other hand, an interval between the contact 11a at the bit line side and the contact 11b at the common source line side, i.e., an interval in the bit line direction (a direction along the line 69—69) is 40F to 100F, for example.
The contacts 11a and 11b are embedded with poly-crystalline silicon in which impurities such as phosphate is doped at a high concentration, and the first wiring layers 12a and 12b are embedded with a metal such as tungsten. The wiring layers 12a and 12b used here are provided as a connecting wiring to a bit line that is longer than 3F in the bit line direction. In the following discussion, a relationship between the wiring layer 12a and the contact 11a will be taken. More generally, a fine metal pattern in a long linear shape may be sufficient. The similar discussion applies to a relationship between the bit line and the contact when the contact 11b is directly connected to the bit line.
In order to ensure a lithography margin, in the case where the contact arrangement pitch is 2F, it is desirable that the diameter of the contact 11a in a circular shape is greater than F, and the wiring width is F. In this case, in a cross sectional view in a direction orthogonal to the wiring layer 12a, the wiring layer width is smaller than the diameter of the contact.
As miniaturization of an element advances, the following problems occur with the prior art of forming the above described contact in accordance with one-time lithography. When the contact is formed by optical lithography one time, of course, a circular or elliptical contact is formed because it is subject to restriction of a spatial frequency caused by a wavelength. A first problem is lowering of a contact lithography margin as shown in FIG. 72A. The circular or elliptical contact is easily short-circuited if a distance between adjacent contacts becomes smaller. Further, in the case of using optical lithography and a positive resist, optical exposure is partially carried out between the contacts. Thus, an exposure quantity increases at a portion at which an interval between the arranged contacts is small so that a pattern loss is likely to occur.
If the contact diameter is reduced in order to prevent this margin lowering, it becomes difficult to open a contact in accordance with lithography. This is because, in comparison with a line/space pattern, in a contact hole pattern, the exposure intensity is reduced so that the exposure sensitivity is lowered, thus making it difficult to open a fine contact while providing a sufficient focal depth and a sufficient exposure variation allowable width. In respect that the spatial frequency of the optical intensity in an arbitrary direction is equal to or smaller than a so called resolution limit, it is obvious that the minimum wiring width of the resolution limit cannot be obtained at the same time in two directions. Therefore, this problem is caused by forming a contact in a circular or elliptical shape with two axis having the substantially the same diameter during lithography.
A second problem is lowering of an alignment margin between the contact 11a and the wiring layer 12a as shown in FIG. 72B. If an interval between the adjacent contacts becomes smaller, the wiring layer is easily short-circuited with the adjacent contact because of a misalignment relevant to the contact of the wiring layer. This problem is caused by separately forming the wiring layer and the contact during lithography.
In addition, conventionally, the contact is subjected to alignment to a ground layer of one layer configuration. For example, when the contacts 11a are aligned to the gate electrodes 5 and 6 (i.e., when direct alignment is carried out), the contacts 11a are indirectly aligned to element regions in a stripe shape orthogonal to the gate electrodes 5 and 6. Therefore, a misalignment between the contact and the element region increases by not less than √2-fold direct alignment, and a contact is formed in the element separation region because of a misalignment between the element region and the contact region. FIGS. 70 and 71 each show a scheme of such a misalignment. If the contacts 11a and 11b exceed an edge of the element separating insulation film 2 and reach a p-type well beneath the n-type diffusion layer 3, a breakdown voltage across the p-type well and the contact material is lowered.
On the other hand, in the case where the contact 11a is aligned to the element region, the gate electrodes 5 and 6 and the contact 11a are directly aligned with each other. Thus, it is required to ensure a great alignment margin in order to prevent a short-circuit between the contact 11a and the gate electrode 6 that is provided as the selection gate line SSL. This causes an increase in length of a memory cell array in the bit line direction and an increase in chip area.
As described above, there has been a problem that, in the conventional wiring contact of the semiconductor device, a lithography margin is reduced, and an alignment margin is reduced along with miniaturization of the contact.